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OSIRIS Technology

Layout Migration

IN2FAB's OSIRIS system uses a patented technique called "complex nodal scaling" to move designs between foundries and geometry size.  After calculating the relationships between the old and new processes, the layout is mapped to the new layers and component types then scaled to an optimum size, completely preserving the hierarchy and topology.
This new layout is then adjusted through a series of manipulation routines to remove DRC violations and adjust component values.

Layout Migration

Working within the Cadence design framework, the tools give the user the flexibility to modify the design at any stage of the migration process and make structural changes to their layout while OSIRIS takes care of data processing and shape based violations.

 

Schematic Migration

In addition to migrating layout, OSIRIS also has the capability to translate schematics from one process to another using foundry models and process design kits.

Symbols and parameters are mapped from source to target process through a clear user interface gives easy access to detailed component description format (CDF) data.

Standard cell library components may also be swapped between schematics and changes in pins and net positions resolved through automatic rewiring through the migration.

Schematic Migration

Process Design Kits

While OSIRIS can work with any GDSII based design, many analog layouts are constructed using parameterized cells from foundry process design kits (PDKs).

OSIRIS features an advanced user interface that automatically finds component values and gives users an easy method of mapping device types and parameters from one process to the next.

Using parameterized cells from the target foundry ensures devices are correct by construction and match the foundry's design criteria.

Process Design KitsProcess Design kits

Key Features
  • Full hierarchy and topology preservation
  • Rapid set-up of rules and devices
  • Simple mapping of layers from source to target process
  • Interactive mapping of parameterized cells and symbolic vias
  • No need for layout or device constraints
  • Layout preserved in the Cadence Virtuoso layout environment
  • Schematic data translated in the Cadence Composer environment


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